Wafer-Level Packaging (WLP) has emerged as a critical enabler for miniaturized, high-performance semiconductor devices. Central to WLP is the Redistribution Layer (RDL), a thin-film metallization scheme that relocates peripheral I/O pads on a die to an area-array layout compatible with standard solder-ball pitch.
- Passivation Opening
The process begins with depositing a dielectric film over the wafer. Openings are then patterned and etched above the original aluminum bond pads to expose them for connection. - Seed-Layer Deposition
A dual-layer metal stack (typically TiW/Cu) is sputtered. The bottom layer acts as an adhesion/barrier, while the top copper layer serves as a conductive seed for subsequent electroplating. - Thick-Resist Lithography
A thick photoresist is applied and exposed using a mask that defines the desired RDL trace pattern. After development, trenches are formed where the copper traces will be plated. - Cu RDL Electroplating
Copper is electroplated into the resist trenches to form the conductive traces. Process parameters are controlled to achieve the target thickness, uniformity, and mechanical properties. - Resist Strip & Seed Etch
The photoresist is removed. Then, the exposed seed metal layers are etched away, leaving only the plated copper traces isolated on the wafer surface. - Secondary Dielectric Deposition
A second dielectric layer is applied to encapsulate and protect the copper traces. Openings are patterned in this layer to create landing sites for external connections (like solder balls). - Micro-Bump Formation (Optional)
For packages requiring vertical interconnection, micro-bumps (e.g., Cu pillars with SnAg caps) can be formed on the exposed landing pads through an additional plating process. - Final Assembly Interface
The wafer undergoes electrical testing and reliability assessment. Upon passing, it proceeds to final packaging steps such as solder ball attachment or molding.
Conclusion
The WLP RDL flow integrates precision lithography, thin-film deposition, and electrochemical metallization to create high-density interconnects at the wafer level. Continued advancement in materials and processes is essential for supporting next-generation heterogeneous integration.
